Verification Future

The Next 5 Years

Tuesday, 15th November 2011

Hilton Hotel, Reading

          The FREE conference will look at the challenges in verification and how these will change over the next 5 years, and attempt to look at some of the solutions

                    For detailed abstracts and biographies please visit our website           (http://www.testandverification.com/files/Agenda.pdf)

          Agenda: All times below are UK times 

          8.30     Arrival: Refreshments and Networking

          9.30     Introduction:  Mike Bartley, TVS

          9.35     Harry Foster, Mentor Graphics          

                     From Volume to Velocity: The Transforming Landscape in Function Verification

          10.20   Panel Session:  Our Top Verification Challenges

                     A view on the verification challenges from some major semi-conductor companies around

                     Europe 

                     Bryan Dickman, ARM (Director Design Assurance, Processor Division)

                     Olivier Haller, STMicroelectronics (Verification Methodology Manager)

                     Hans Lundén, Ericsson

                     Clemens Muller, Infineon

          11.00   Refreshments and Networking

          11.30   Mike Stellfox, Cadence Design Systems 

                     The next frontier - Addressing the Challenges of SoC Verification 

          12.00   Serrie Chapman and Darren Galpin, Infineon Technologies 

                     The drive for Requirements Engineering and how it may affect verification

          12.20   Mike Benjamin, TVS 

                     Benchmarking Functional Verification

         12.40    Steve Holloway, Dialog Semiconductor 

                      “Adopting a Methodology”, How and why?

          13.00   Lunch and Networking

          14.00   Lawrence Loh, Jasper Design Automation 

                     SOC-level Formal Verification

          14.30   Nick Gatherer, ARM 

                     Does ESL Have a Role in Verification?

          15.00   Jean-Marc Forey, SpringSoft 

               Mutation-based Testing Technologies Close the “Quality Gap” in Functional Verification for

                     Complex Chip Designs

          15.30   Refreshments and Networking

          16.00   Janick Bergeron, Synopsys 

                     Title to be determind

          16.30   Panel Session:  The EDA response

          17.15   Refreshments and Networking

          This event is sponsored by

Mentor Graphics, SpringSoft, Cadence, Jasper, Synopsys and TVS

          I understand that photographs and videos of me may be taken during this event. I give my permission to use these in any promotional materials for MathWorks. We will not sell or rent your personal contact information. See our privacy policy for details. 

          TVS would like to share your name and contact details with the companies that present and sponsor the conference.  If you do not consent please contact Sara Horrell (sara@tandvsolns.co.uk) and request to be excluded.

Thank you.